Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured.
An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, DCMs may be used to perform various clock related functions, such as multiplying/dividing clock frequencies to synthesize new frequencies, mitigating clock skew, condition clock signals to maintain specified duty cycles, and the like. Some clock functions of a DCM, such as a clock deskew function, require both a reference clock and a feedback clock as input. The feedback clock is typically a clock output by the DCM, but including delay added by a clock distribution network in the FPGA. Thus, the feedback clock is obtained from some point on the clock distribution network. If the feedback clock input to the DCM is lost (e.g., due to some problem with the clock distribution network), the DCM will not be able to properly perform the clock deskew function. However, the user's design programmed in the FPGA will operate under the assumption that the deskew function is being performed, which may result in various logic errors. Accordingly, there exists a need in the art for a method and apparatus for detecting clock loss in a digital clock manager.